Clp, automation, postlayout STA, LINT, prelayout STA, Synthesis, cdc, SDC generation, demotion, AI scripting, SDC development, LEC, RTL Netlist based static checks, Timing Closure, promotion, Verification, equivalence checking

Signal Integrity, SDC constraints, MCMM, MMMC, setup hold analysis, timing optimization, timing ECOs, Timing Analysis, Cadence Tempus

Test Automation, Signal Integrity, electromagnetic compatibility, Circuit Design, DFT Techniques, Simulation Tools, Debugging Skills, Pcb Design, Data Analysis, Documentation

STA Engineer, Timing Lead, primetime, PT-DMSA, OCV/AOCV/POCV, Signal Integrity, TCL scripting skills, Tempus, ECO generation, PNR

monte carlo , Perl, Python, Tcl, FineSim, Hspice, PT Tempus, Spice, Layout Parasitic Extraction, Signal Integrity, ICC, digital flow design, RTL to GDS, primetime, Innovous, ASIC back-end design flows, STA setup, Timing Analysis

Scripting, Clp, Automation, LINT, cdc, Prelayout STA, SDC generation, SDC development, LEC, Low power aspects, RTL Netlist based static checks, Timing Closure, Synthesis, Postlayout STA, Timing Constraints

Clp, Automation, SDC constraints development, Synthesis, Timing Closure, LINT, LEC, AI scripting, Prelayout STA, cdc, Postlayout STA, RTL Netlist based static checks, SDC generation

synopsys primetime , Tcl, Python, Perl, ECO Implementation, Cadence Tempus, Constraint Management, Signal Integrity

Timing ECO Implementation, LVF POCV variation formats, digital design Implementation, RTL to GDSII, Timing Analysis, Timing Closure, CTS strategies, STA setup, Cadence Tools, Tweaker Prime Time based ECO flows, Automation scripts, Constraint development