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STA Engineer
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- Posted 13 days ago
- Over 50 applicants have applied
Job Description
Role : STA Engineer
Exp : 10+ Years
Work Location : Bangalore
Industry : Semiconductor
Description
We are seeking an experienced STA Engineer to join our team in India. The ideal candidate will have 10-20 years of experience in testing and validation of electronic components, with a strong focus on developing effective test strategies and ensuring high quality in our products.
Responsibilities
- Design and develop test strategies for various electronic components and systems.
- Conduct testing and validation to ensure compliance with specifications.
- Analyze test data and prepare detailed reports on findings and recommendations.
- Collaborate with cross-functional teams to identify and resolve technical issues.
- Maintain and enhance testing equipment and environments.
Skills and Qualifications
- Bachelor's degree in Electronics Engineering, Electrical Engineering, or a related field.
- Proficiency in test automation tools and methodologies.
- Strong understanding of electronic circuits and systems.
- Experience with programming languages such as Python, C/C++, or MATLAB.
- Familiarity with industry standards for testing and quality assurance.
- Excellent problem-solving and analytical skills.
- Strong communication and teamwork abilities.
More Info
Key Skills
About Company
Skills:
Signal Integrity, SDC constraints, MCMM, MMMC, setup hold analysis, timing optimization, timing ECOs, Timing Analysis, Cadence Tempus
Skills:
STA Engineer, Timing Lead, primetime, PT-DMSA, OCV/AOCV/POCV, Signal Integrity, TCL scripting skills, Tempus, ECO generation, PNR
Skills:
monte carlo , Perl, Python, Tcl, FineSim, Hspice, PT Tempus, Spice, Layout Parasitic Extraction, Signal Integrity, ICC, digital flow design, RTL to GDS, primetime, Innovous, ASIC back-end design flows, STA setup, Timing Analysis
Skills:
DDR/LPDDR/HBM, Timing Closure, Cross-functional Collaboration, Memory PHY Architecture, Signal Integrity, Mixed Signal Design
Skills:
Formal verification (LEC), Static Timing Analysis (STA), Hierarchical synthesis flows, power analysis, SystemVerilog RTL, Logic Synthesis, Physical-Aware Synthesis, Signal integrity analysis, PPA optimization, Floorplan-driven synthesis, UPF management