Routing, Perl, Static Timing Analysis, Tcl, CTS, Cadence, LVS, Optimization, CAD Tools, Dfm, Parasitic Extraction, Physical Verification, Synthesis, PNR, Placement, DRC, Floor Planning, Mentor Graphics, Clock Tree Synthesis, IR drop analysis, Synopsys, GDSII

Unix, python, perl, Linux, Tcl, Calibre, Back-End physical design EDA tools, large scale ASIC chip physical design, deep submicron ASIC design flow, Fusion Primetime

Tcl, Python, Perl, routing, Innovus, Timing Constraints, LVS, CTS, Sta, ICC2, Physical Design, primetime, Tempus, MCMM analysis, DRC, PNR, SDC

routing, Perl, Python, Tcl, Netlist to GDSII, power delivery IR-drop, Tempus, Cadence Innovus, LVS, Physical Verification, Floor Planning, Signal Integrity, primetime, Asic Physical Design, antenna checks, ERC, Timing Closure, DRC, Placement

Unix, Automation Scripting, Shell, Perl, Verilog, Python, Tcl, power analysis, Low-Power Design Strategies, VHDL, Physical Design, EDA Tools

Tcl Scripting, PNR Timing closure, Physical signoff, Fusion Compiler, Innovus