Power Integrity and Power Delivery Network design, Debug test and characterization, Test pattern test flow development, Frequency domain measurement, Time domain power noise measurement

bist , Java, Unix, C, Windows, Jtag, Perl, Linux, Version Control Systems, Ruby, Python, statistical analysis techniques, HSIO, ATE development, modern computer architecture, Advantest 93K

CMT HMDT test module conversion, coverage analysis, silicon debug, DFT Design-for-Test, test vector generation, ATE program development

Debug infrastructure, Statistical Modeling, Data automation, Silicon Characterization, Test content strategies, Yield analysis, Production analytics pipelines

C, Perl, Verilog, Python, Tcl, Statistical Analysis, on-chip interconnects, systemverilog, Ate, VHDL, EDA Tools, Embedded Systems

Power Integrity and Power Delivery Network design, Debug test and characterization, Test pattern test flow development, Frequency domain measurement, Time domain power noise measurement