Noc, Verilog, Debugging, Sta, cdc, clock reset, Simulation, Rtl Design, RDC, waveform analysis, DMA, register design, silicon bring-up, formal equivalence checking, Synthesis, memory subsystem, SOC design, Emulation, ASIC implementation, systemverilog, Axi, APB, LINT, Timing Closure, low-power checks, AHB

C, Soc Architecture, Windows, Encryption, Perl, Linux, Hypervisor, Debugging, Microprocessor Cores, Python, validation methodologies, validation infrastructure, platform security, secure boot

Verilog, Digital design fundamentals, Axi, SoC integration methodologies, APB, Lint methodologies, AMBA protocols, AHB, Synthesis tools, systemverilog, Timing Analysis

Pcb Design, DFA, Dft, Design Verification, IPC standards, Pads, Circuit Analysis, Simulation, Dfm, PCB library components

C, Soc Architecture, Windows, Encryption, Linux, Perl, Hypervisor, Microprocessor Cores, Python, validation methodologies, validation infrastructure, secure boot, platform security

C, Verilog, Python, LabVIEW, ALLEGRO, 3D field solvers, Cadence Concept Schematic Capture, Spice, Verilog simulators

bist , Ovm, shell scripting, PERL, System Verilog, debug flows, DFD, ATPG tools, TAP, Mentor Graphic Tessent, STF, BSCAN, DFX strategy, Uvm, Spyglass-DFT, MemoryBIST, Synopsys VCS, Dft, DFV, RTL Coding, Scan, automation concepts