routing, power distribution planning, LEC, MBR flows, Floor Planning, design tools and flows, Low Power physical design flows, Power-Gating, clock network planning, Timing Closure, Clock-Gating, placement and optimization

rc extraction , Timing ECO Implementation, Physical Design, Timing ECOs, Placement, floorplanning, Timing Closure, Routing and Optimization, Full-chip and Block-level Physical Implementation

power integrity , UNIX, routing, Linux, Perl, Verilog, Shell scripting, Tcl, Cadence PVS, floorplanning, LVS closure, Cadence Innovus, Cadence ETS, Signal Integrity, Physical Verification, VHDL, Synopsys ICC, RTL-to-GDSII implementation, Timing Closure, DRC, Placement

Shell, PYTHON, Static Timing Analysis, Tcl, Flex-H, power analysis, STA constraints, FinFET Dual Patterning nodes, Innovus, Physical Design, PD metrics dashboard scripts for QOR tracking, PNR flow from RTL to GDS flow, Multi-point CTS, Custom-CTS

layout verification , static timing analysis, routing, Synthesis, coverage analysis, electrical rule checking, formal equivalence verification, Power Clock Distribution, physical design implementation, structural design checking, physical clock design, Place And Route, power and noise analysis, placing, static and dynamic power integrity, RTL to GDS, Floor Planning, Dft, EDA Tools, Timing Closure, multiple power domain analysis, Clock Tree Synthesis

synopsys primetime , Asic Physical Design, Cadence innovus, Synopsys

static timing analysis, place-and-route, Synthesis, SDC development, RTL-to-GDS tools and methodologies, EDA tools and flows, Floor Planning, primetime, timing budgeting, multi-power domain analysis, low-power design techniques, timing signoff, Clock Tree Synthesis

power integrity , DDR, Python, Routing, Perl, Tcl, IR drop, Signoff, primetime, Cadence Innovus, LVS, Timing Closure, SERDES, StarRC, Placement, Signal Integrity, Power Planning, floorplanning, Physical Verification, PNR, Physical Design, Timing congestion, DRC, PPA optimization, Reliability, Synopsys ICC2