hardware engineering , Digital Logic Design, Embedded Firmware, Scripting Languages, Jtag, Verilog, System Verilog, IEEE1500, Micro-processor debug, Power management verification, Memory dump, MBIST, UPF, C Language, Scan dump, DFT architecture

Python, scoreboarding, Mentor Questa, Cadence Xcelium, AXI protocol, GLS, SystemVerilog UVM, Synopsys VCS, memory controller architecture, assertions SVA, DDR protocol JEDEC specifications, functional coverage

Python, scoreboarding, Mentor Questa, Cadence Xcelium, AXI protocol, SystemVerilog UVM, GLS, Synopsys VCS, memory controller architecture, assertions SVA, DDR protocol JEDEC specifications, functional coverage

cache coherency , Vcs, Perl, Python, Tcl, CHI, Ace, Xcelium, GPU Verification, AMBA protocols, NoC Integration, coverage-driven verification, SystemVerilog UVM, constrained-random verification, Performance Validation, Axi, Questa, SVA assertions

C, Systemc, Algorithm Development, Technical Leadership, MATLAB, Verilog, Python, Research Innovation, Cross-Functional Collaboration, System-Level Power Estimation, VHDL, Simulink, system modeling, Methodology Development

Ethernet, Pcie, Synopsys, Uvm, advanced verification methodologies, systemverilog, Mentor, Cadence, PAM4, Register modeling, D2D, protocol VIP integration, Avery, PAM2

Functional coverage, Assertions SVA, Timing Constraints SDC, Physical Design PD, Uvm, Rtl Design, SystemVerilog SV, Verification

Tcl, Vcs, Python, Perl, Version Control, assertion-based verification, Questa, Uvm, verification methodologies, systemverilog, CI CD, RTL simulation, functional coverage