Defect Tracking, Verilog, Test Planning, coverage analysis, RTL simulation, regression management, digital logic design concepts, interface protocols, Uvm, systemverilog, Verification Tools, formal verification, VHDL, EDA Tools, FPGA architectures, design verification methodologies

PERL, System Verilog, Python, Uvm, verification tools and methodologies

C, Makefile, Perl, C Shell, Verilog, Ruby, Oscilloscopes, Uvm, systemverilog, design verification methodology, Synopsys VC Verification IP VIP for USB, USB traffic generators and checkers

Linux, Windows, IP level ASIC verification, UVM based verification frameworks, UVM testbenches, systemverilog