power integrity , Static Timing Analysis (STA), Python Scripting, MCMM analysis, floorplanning, Netlist to signoff GDSII, CTS routing, Cadence Innovus, Physical design signoff, ECO implementation, Timing Closure, Timing constraints setup hold closure, Placement, Full-chip physical design flow

IR EM Analysis, SI PI Analysis, STA and Timing Closure, Cadence, Tcl Python Scripting, Clock Architecture and CTS, Advanced Node Design Methodologies, AI-assisted Design Flows, Floorplanning and Power Planning, Physical Verification, Low Power Design UPF CPF, Physical Design and Signoff, Synopsys

test systems , Clock Tree Synthesis (CTS), Unix, Fpga, Clp, Linux, Perl, Packaging test systems, Yield circuits, floorplanning, power analysis, Optical systems, LEC, PNR implementation, Mechanical Systems, DSP systems, Signoff knowledge, Low power verification, Placement, PDN

AI based EDA tools, HBM HMC memory systems, Fusion Compiler, floorplanning, Cadence Innovus, Partitioning strategies, PPA strategy, UPF, Implementation methodologies, TSMC Tech Node, Signoff methodologies, Congestion strategies, QoR assessments, GDS-II, Physical Design, Large SoCs, Synopsys ICC2, Multi-voltage designs

SystemVerilog Assertions (SVA), C, C++, UNIX, MATLAB, Continuous Integration, Perl, Verilog, Shell scripting, Python, Tcl, AI/ML based computer vision algorithms, API Architecture Design, Uvm, AMBA interfaces, systemverilog, VHDL, Project Management, Image processing algorithms, DDR specifications, ASIC RTL design

static timing analysis, Perl, Verilog, Python, Tcl, Rtl Design, Synthesis, Dft, ATPG, systemverilog

System Testing, Robot Framework, Ipv4, Spirent, L2vpn, L3vpn, Ipv6, Ixia, VLAN, BGP, Qos, Ldp, Rsvp, OSPF, Python, Networking Systems Engineering, Solution Validation, IS-IS, Junos EVO, Mpls

IO Bump PV cleanup, Antenna Density DFM DFY DPT, Die file generation, SoC Full-chip floorplanning, Package PV checks, Bump planning, Metal layers usage maximization

Automation Frameworks, Perl, Python, Tcl, AI-native automated methodologies, Methodology, Physical Design, Sub-3nm device physics