Calibre, Mixed Signal Layout, Physical Verification, Analog Layout, DRC, Custom Layout, virtuoso, LVS, Chip Level Integration, CAD Tools, Layout Electrical Parameters

Routing, Mixed-Signal Layout Design, Mentor Siemens Calibre, Device-Level Layout, floorplanning, Cadence Virtuoso, Parasitic Extraction

FinFET technologies, Calibre, Mixed-Signal Layout, pegasus, DRC, Physical Verification, LVS, Analog Layout Design, Cadence Virtuoso

manufacturing processes , assembly processes , product life cycle , Plm, project management, tolerance stack-up analysis, materials selection, production costing, product design development, CAD Tools, quality value engineering, supply chain optimization, Creo, industrial costing, Pdm

Signal integrity considerations, Analog Layout Design, Parasitic Extraction, Power distribution techniques, Analog circuit design principles

bandgap references , power FETs, Schmitt Trigger, Monte Carlo analysis, Pspice, mismatch noise gain offset, Statistics, Amplifiers, ESD protection circuits, Level Shifter, transistor layout fabrication process, Analog Circuit Design, transistor level architectures, LDMOS, Comparators, Current Mirrors, Statistical Distributions, MOS Diodes

Sta, power analysis, PDN analysis, CTS, Physical Verification, Dfm, Physical Design, Timing Closure, ASIC Implementation, Dft, Synthesis, Timing Closure, Floor Planning, logical and physical optimization, Structured clock tree, Place And Route

Uart, Spi, Pcie, Python, Tcl, Cadence-Xcelium, DO-254, ARINC 818, VHDL, Rivera-PRO, AXI4, Synopsys-VCS, Siemens-Questasim