Signal Integrity, SDC constraints, MCMM, MMMC, setup hold analysis, timing optimization, timing ECOs, Timing Analysis, Cadence Tempus

STA Engineer, Timing Lead, primetime, PT-DMSA, OCV/AOCV/POCV, Signal Integrity, TCL scripting skills, Tempus, ECO generation, PNR

monte carlo , Perl, Python, Tcl, FineSim, Hspice, PT Tempus, Spice, Layout Parasitic Extraction, Signal Integrity, ICC, digital flow design, RTL to GDS, primetime, Innovous, ASIC back-end design flows, STA setup, Timing Analysis

DDR/LPDDR/HBM, Timing Closure, Cross-functional Collaboration, Memory PHY Architecture, Signal Integrity, Mixed Signal Design

Formal verification (LEC), Static Timing Analysis (STA), Hierarchical synthesis flows, power analysis, SystemVerilog RTL, Logic Synthesis, Physical-Aware Synthesis, Signal integrity analysis, PPA optimization, Floorplan-driven synthesis, UPF management