STA Engineer
- Posted a month ago
- Be among the first 40 applicants
Job Description
- Define the architecture of Memory PHY IPs, its major blocks
- Responsible to develop the architecture and create specification for clocking, ASIC interface, pin-outs, bump-outs, floor plans, functionalities to support the protocol/system level requirements, Digital/Analog/Firmware Interface and partitions, calibration and other algorithm definition, test/debug logic etc
- Work with cross-functional teams and technical experts in various geographies to define and align scope of the IPs
- Support marketing on presales activities technically
- Be the interface to the customer in technical interactions, feasibility analysis, interoperability definitions and tracking
- Understand and disseminate applicable standards and its relevance in a given project to the team
- Provide definitions of scope and review the plans of verification team
- Work with the system engineering team for Silicon bring up and Characterization.
Skills/Qualifications:
- MS/M-Tech degree in electronics/VLSI and in exceptional cases B.E/B-Tech in electronics engineering with 10 years of relevant experience needed.
- The candidate should have prior experience of working on mixed signal designs, Signal Integrity analysis, Digital and Analog design, timing closure and simulation.
- Experience in designing memory systems such as DDR, LPDDR, GDDR, HBM
- Experience in architecture or micro-architecture development.
- Experience working with customers and cross-functional teams
- Experience working in leading RD and future technology development projects is desirable.
- The position requires good written verbal communication skills as well a strong commitment and ability to work in cross functional and globally dispersed teams.
More Info
Key Skills
DDR/LPDDR/HBM
Cross-functional Collaboration
Memory PHY Architecture
About Company
Alp Consulting, one of the leading recruitment and staffing companies of India, is a ISO 9001:2000 certified company and a subsidiary of Outsourcing Inc., a multi-billion-dollar Japanese conglomerate with presence in 17 countries.
Skills:
Clp, automation, postlayout STA, LINT, prelayout STA, Synthesis, cdc, SDC generation, demotion, AI scripting, SDC development, LEC, RTL Netlist based static checks, Timing Closure, promotion, Verification, equivalence checking
Skills:
Signal Integrity, SDC constraints, MCMM, MMMC, setup hold analysis, timing optimization, timing ECOs, Timing Analysis, Cadence Tempus
Skills:
Test Automation, Signal Integrity, electromagnetic compatibility, Circuit Design, DFT Techniques, Simulation Tools, Debugging Skills, Pcb Design, Data Analysis, Documentation
Skills:
STA Engineer, Timing Lead, primetime, PT-DMSA, OCV/AOCV/POCV, Signal Integrity, TCL scripting skills, Tempus, ECO generation, PNR
Skills:
monte carlo , Perl, Python, Tcl, FineSim, Hspice, PT Tempus, Spice, Layout Parasitic Extraction, Signal Integrity, ICC, digital flow design, RTL to GDS, primetime, Innovous, ASIC back-end design flows, STA setup, Timing Analysis