Perl, Python, Tcl, Synopsys VC Formal, register verification, formal coverage, Cadence JasperGold, Uvm, equivalence checking, systemverilog, FPV connectivity checking

Fpga, Ovm, DDR, Pcie, Ethernet, Cadence, Uvm, assertion-based verification, ARM architectures, systemverilog, HSST, Mentor Graphics, Synopsys, constrained random verification methodologies

Git, Perl, Python, Tcl, Functional Coverage, Regression Automation, Uvm, systemverilog, SVA

C, Perl, Pcie, Verilog, Ruby, Python, coverage-based verification methodology, PSL, Uvm, systemverilog, IOMMU, SVA, hardware assertions, hardware verification methodologies