Senior Design Verification Engineer

Responsibilities:

• Perform pre-Si verification on various IP blocks and full-chip of FPGA/ASIC designs.
• The job scope includes test plan definition, SystemVerilog/UVM test bench and content development, debugging and running regression to deliver good-quality design.
• Candidate will work closely with team and interact with product/IP architect, logic design engineer, DFX owner, and design automation engineer to ensure high quality design validation.

Qualifications:

• BSEE/MSEE/PhD with at least 4 years relevant experience
• Experience in functional verification that may includes test planning, test bench development, stimulus generation, reference model and assertion checkers development and functional coverage.
• Experience with modern verification techniques e.g. SystemVerilog OVM/UVM, assertion-based verification, constrained random verification methodologies.
• Familiar with IP protocols (e.g. HSST, Ethernet, PCIe, DDR), FPGA and/or ARM architectures.
• Hands-on experience in various logic designs and verification tools and flow e.g. from Cadence, Mentor Graphics and/or Synopsys.