Java, Api Management, Azure Functions, Data Integration, Azure Cloud Integrations, Logic Apps, Service Bus, Event Grid, Azure Monitor, Microservices Architecture

Technical Leadership, Soc, ASIC implementation, custom IP integration, physical design flows, custom silicon design, hardware-software co-design, mass production, system-level debug, silicon bring-up, SoC development programs, hardware-software co-design principles, root-cause analysis

clocking , Verilog, EDA tools for synthesis, LINT, Use of AI for design, cdc, SoC-level design and integration, Synthesis flows, Rtl Design, spyglass, VHDL, Verification methodologies, RDC, Digital design principles, Resets, Timing Constraints, Micro-architecture design, Low-power design techniques, Timing Analysis

consumer insight , Creative Direction, brand architecture, Customer Experience, Brand Communication, App UX, Performance Marketing, Brand Strategy

power integrity , Static Timing Analysis (STA), Python Scripting, MCMM analysis, floorplanning, Netlist to signoff GDSII, CTS routing, Cadence Innovus, Physical design signoff, ECO implementation, Timing Closure, Timing constraints setup hold closure, Placement, Full-chip physical design flow

Software Development, Apache Flink, Apache Kafka, Apache Druid, OpenSearch, distributed systems design

SystemVerilog Assertions (SVA), C, C++, UNIX, MATLAB, Continuous Integration, Perl, Verilog, Shell scripting, Python, Tcl, AI/ML based computer vision algorithms, API Architecture Design, Uvm, AMBA interfaces, systemverilog, VHDL, Project Management, Image processing algorithms, DDR specifications, ASIC RTL design

System Testing, Robot Framework, Ipv4, Spirent, L2vpn, L3vpn, Ipv6, Ixia, VLAN, BGP, Qos, Ldp, Rsvp, OSPF, Python, Networking Systems Engineering, Solution Validation, IS-IS, Junos EVO, Mpls

Perl, Python, Tcl, Power integrity analysis, Cadence Voltus, Ansys RedHawk, Static and dynamic IR analysis, Power grid optimization