Logic Design, routing, Circuit Design, floorplanning, LVS, Physical Verification, Physical Design, EDA Tools, Timing Closure, DRC, Placement, Clock Tree Synthesis, Rtl Design

Routing, Post route optimization, Clock gating, floorplanning, Low power design techniques, Power gating, Timing Closure, Placement optimization, CTS Clock Tree Synthesis, DFT Test, RTL Micro architecture, Automation scripts flows, SI Crosstalk, STA Primetime, Foundry and CAD, Multi Vt Multi voltage UPF, Advanced nodes 7nm 5nm 3nm or below, Methodology improvements, Physical verification and signoff, IR drop EM analysis, Power planning PG grid IR

Perl scripting, Cadence EDI, Mentor Calibr, Design Automation, RTL-to-GDSII process flow, Synopsys ICC design flow