Perl scripting, Verilog, Cadence EDI, Sta, Design Automation, Mentor Calibre, Physical Verification, Close tree synthesis, Gate level netlist to GDS design, Foundry merge, Timing sign off, Place Route, Synthesis, Dft, Synopsys ICC, Floorplan, IR drop analysis

Routing, Post route optimization, Clock gating, floorplanning, Low power design techniques, Power gating, Timing Closure, Placement optimization, CTS Clock Tree Synthesis, DFT Test, RTL Micro architecture, Automation scripts flows, SI Crosstalk, STA Primetime, Foundry and CAD, Multi Vt Multi voltage UPF, Advanced nodes 7nm 5nm 3nm or below, Methodology improvements, Physical verification and signoff, IR drop EM analysis, Power planning PG grid IR

Perl, Python, Tcl, LabVIEW, Oscilloscope, EDA Tools, VLSI Design Flow, Multimeter