Physical Design Engineer
Physical Design Engineer
alchip technologies- Posted a day ago
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Job Description
Job Description
- Perform gate level netlist to GDS design independently including but not limited to floor planning, place & route, close tree synthesis, timing sign off and physical verification.
- Perform design IP Implementation, IR drop analysis, DFT, STA and foundry merge.
- Work with manager to achieve assigned tape out target.
Qualifications
- Bachelor or MS Degree in EE or related.
- Must has solid knowledge on digital/analog electrical; knowledge on verilog/ synthesis/ floorplan will be a plus.
- Experience of working on top level design with chip level floor plan is a plus.
- Familiar with Cadence EDI, Synopsys ICC design flow and Mentor Calibre for physical design engineer.
- Familiar with TCL/ Perl scripting and design automation.
More Info
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Key Skills
Cadence EDI
Mentor Calibre
Close tree synthesis
Gate level netlist to GDS design
Foundry merge
Timing sign off
Synopsys ICC
IR drop analysis
About Company
Skills:
Logic Design, routing, Circuit Design, floorplanning, LVS, Physical Verification, Physical Design, EDA Tools, Timing Closure, DRC, Placement, Clock Tree Synthesis, Rtl Design
Skills:
Routing, Post route optimization, Clock gating, floorplanning, Low power design techniques, Power gating, Timing Closure, Placement optimization, CTS Clock Tree Synthesis, DFT Test, RTL Micro architecture, Automation scripts flows, SI Crosstalk, STA Primetime, Foundry and CAD, Multi Vt Multi voltage UPF, Advanced nodes 7nm 5nm 3nm or below, Methodology improvements, Physical verification and signoff, IR drop EM analysis, Power planning PG grid IR
Skills:
Perl scripting, Cadence EDI, Mentor Calibr, Design Automation, RTL-to-GDSII process flow, Synopsys ICC design flow