Usb, Fpga, Pcie, Perl, Python, verification methodologies, Emulation, coverage driven verification, directed constrained-random tests, Uvm, systemverilog, MIPI, formal verification, AMBA, Test Bench, transaction level modeling, AXI4

Verilog, System Verilog, Assertion Checker Development, Coverage Closure, Functional Coverage Development, Testcase Planning Development, UVM Testbench Coding, IP SOC Verification, Design Verification Failure Debugging, Concepts in Digital Design

Pcie, System Verilog, Python, Systemc, Hybrid test benches, MDV, DV signoffs, SV, Uvm, UCIe, Axi, CDV

Shell, Perl, Python, Tcl, Cadence Xcelium, Mentor QuestaSim, PCI Express, Uvm, systemverilog, Synopsys VCS, Assertion-Based Verification, Constrained Random Verification, Functional Verification

C, Pcie, Perl, Python, Tcl, UFS, HSIO PHY Controllers, Skill, Open Verification Methodology, USB2, systemverilog, MIPI, USB3, Universal Verification Methodology

Design Verification, Debugging RTL Verilog designs

DDR, Ethernet, System Verilog, RISC-V cores, SV coverpoints, GIC, CMN, AXI protocol, SMMU, Low-power verification, PCle, Cache and coherency verification, Uvm, UPF, ACE protocol, eMMC, CoreSight, Low-speed peripherals, ARM v8 and v7 cores, Assembly

Perl, Python, Tcl, Functional Coverage, Uvm, SVA, systemverilog, ASIC SoC Subsystem IP verification

Pcie, Regression Testing, Verilog, Ethernet, assertions, Uvm, systemverilog, functional coverage, constrained-random verification