SystemVerilog Assertions (SVA), Context Protocol (MCP), Large Language Models (LLMs), Git, Linux, Verilog, Python, LangChain, CrewAI, Generative AI, RTL design methodologies, UVM-based verification, systemverilog, scripting automation, LangGraph, AutoGen

Git, Linux, Verilog, Python Programming, Generative AI, Prompt engineering, RTL design methodologies, LLMs, Cloud AI platforms, AI agent workflows, Functional coverage, systemverilog, Assertions, UVM verification, Scripting automation, AI-assisted software development tools, SVA, RAG architectures, Simulation debug tools

System Verilog, C, C++, Python, Verification Tools, Uvm

C Programming, Debugging, Problem-solving, SoC-level verification, UVM-based verification environments

assertion based verification , Debugging Tools, Scripting Languages, systemverilog, Uvm, Testbench Development, FPGA Prototyping, coverage analysis, Design Simulation, Design Verification, Asic verification, SoC Verification