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Analog Mixed Signal Layout engineer
Skillsets
1. Serder IO , DDR IO , or any high speed IO
2. PLL, DLL
3. LDO, Bandgap, power-delivery simulation
4. Pure analog circuit
5. IO floorplan, power delivery planning
6. IO ESD layout and analysis
7. C4 bump, RDL experience
8. Cadence layout tools
Past experience:
1. Advanced process node layout rule, at least <= 7nm process
2. With past Samsung <= 5nm layout experience is a strong plus
Job ID: 151306587
Skills:
shielding , IR drop, Common-centroid layout, Cadence layout tools, LVS, Power delivery planning, DLL layout implementation, Noise isolation, ERC, DRC, Guard rings, Device matching, Symmetry
Skills:
Dll, Pll, DDR IO, Serder IO, analog design timing analysis, LDO, ADE Cadence tools, Analog RTL modeling, Pure complex analog circuit, Bandgap power-delivery simulation, high-speed clk distribution, high speed IO
Skills:
C4 Bump and RDL Experience, LDO Bandgap and Power Delivery Simulation, SerDes IO DDR IO or other High-Speed IO layouts, Cadence Layout Tools, Pure Analog Circuit Layout, PLL and DLL layouts, IO ESD Layout and Analysis, IO Floor planning and Power Delivery Planning