Design Verification Engineer
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Job Description
4+Years Strong experience in System Verilog and UVM methodology
Hands-on expertise in high-speed interface protocols (PCIe / USB / DDR / Ethernet / AXI, etc.)
Good understanding of verification concepts, coverage, assertions, and debugging
Experience with simulation tools (VCS, Questa, Xcelium, etc.)
Strong analytical & problem-solving skills
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Key Skills
About Company
Skills:
SystemVerilog Assertions (SVA), test environments , Gate-Level Simulation (GLS), Test Cases, Low power debug, Constrained-random verification environments, Uvm, systemverilog, Verification test benches, Formal tools, Verification methodologies, Coverage measures, formal verification
Skills:
code coverage , perl, Regression Testing, Ovm, Ethernet Protocols, Python, multiple RTL simulators, X-propagation, Uvm, systemverilog, functional coverage
Skills:
Testplan, Perl, Verilog, Shell scripting, Python, System Verilog, testbench, Pre-silicon verification, Coverage Assertion writing, Uvm
Skills:
Design-for-Debug (DFD) and Verification Debug, Verilog, Usb, Pcie, UVM-based Verification Environment Development, Verification Planning Execution, SoC Subsystem Verification, Testbench Development, Interconnect Verification, systemverilog, Functional Coverage, UFS, Axi, Assertions SVA, EMAC Ethernet, Coverage-driven Verification, AHB, AMBA ATB Protocols
Skills:
Version Control Systems, Computer Architecture, Soc Architecture, Simulators, coverage analysis, Formal Verification Techniques, Constrained Random Testing, PCIe Protocol Concepts, Advanced Debugging, Simulation Failures, Waveform Analysis, Root-Cause Identification, Functional Verification, Testbench Development, EDA Tools, Verification Planning, Rtl Design