As a core member of the verification team, you will be responsible for building robust verification environments and performing advanced verification strategies to ensure the functionality, reliability, and performance of IP, block-level modules, and SoC products.
This role offers you the opportunity to dive deep into cutting-edge technologies such as UVM, constraint random verification, and high-speed serial interfaces(Such as: PCIe/USB).
Responsibilities :
Develop and execute verification plans for IP, block-level, and SoC products, ensuring comprehensive coverage of design functionalities.
Build and optimize verification environments (testbench) including scoreboard, monitor, and agent at both IP and SoC levels, realizing efficient reuse of IP-level verification components.
Construct block-level modules when required to support the smooth progress of verification work.
Apply Verilog/SystemVerilog and UVM methodologies to implement coverage-based verification and constraint random verification, ensuring thorough validation of design specifications.
Explore and apply advanced verification methods; participate in formal property verification work if applicable.
Collaborate with design engineers to analyze and resolve verification issues, ensuring the timely delivery of high-quality chip designs.
Engage in the verification of high-speed serial interfaces such as PCIe and USB, ensuring their stable and reliable operation.
Qualifications :
Good understanding of Verilog / System verilog.
Good understanding on UVM, coverage based verification and constraint random verification.
Knowledge of building verification environment - test bench (scoreboard, monitor, agent) at IP and SoC level (reuse from IP level) building of block level module when needed.
Advance verification methods - formal property verification is a plus.
Exposure to high speed serial interfaces such asPCle and USB.
