Design Verification Engineer
- Posted 16 days ago
- Be among the first 10 applicants
Job Description
Job Responsibilities:
- Be part of a team verifying complex IPs and driving them to closure against challenging milestones.
- Build verification environments and UVM/OVM testbenches based on chip requirements.
- Work across RTL, power-aware, and gate-level verification.
Requirement:
- Bachelor's degree (or higher) in Electrical/Electronic Engineering or related.
- 3-6 years of handson experience in digital IP verification using SV/UVM or similar methodologies.
- Solid knowledge of ASIC verification concepts.
- Bonus if you've dabbled in scripting (Perl/Python) or have database knowhow.
- Willing to relocate and work in Penang, Malaysia
More Info
About Company
Skills:
Git, Linux, Verilog, Python Programming, Generative AI, Prompt engineering, RTL design methodologies, LLMs, Cloud AI platforms, AI agent workflows, Functional coverage, systemverilog, Assertions, UVM verification, Scripting automation, AI-assisted software development tools, SVA, RAG architectures, Simulation debug tools
Skills:
System Verilog, C, Python, Debugging, C++, System simulation models, Uvm, Test benches, FPGA design verification, Verification tools and methodologies, IP verification plans
Skills:
C Programming, Debugging, Problem-solving, SoC-level verification, UVM-based verification environments
Skills:
Tcl, Python, Perl, formal coverage, Uvm, Cadence JasperGold, Synopsys VC Formal, systemverilog, FPV connectivity checking, register verification, equivalence checking
Skills:
Tcl, Jtag, Python, Perl, Git, SVA, MBIST, Uvm, DFT Architectures, Functional Coverage, systemverilog, Regression Automation, Scan, LBIST