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Principal Physical Design Engineer (6–10 Years)
Role Summary:
We are seeking a Principal Physical Design Engineer with 5 –10 years of ASIC physical design experience. The role involves driving the complete physical design flow from floorplanning to GDSII signoff, ensuring timing, power, area (PPA), and quality targets are achieved. You will also contribute to design methodology improvements and mentor junior engineers.
Key Responsibilities:
Required Skills & Qualifications:
To apply, send your resume at [Confidential Information]
Job ID: 151253277
Skills:
power integrity , UNIX, routing, Linux, Perl, Verilog, Shell scripting, Tcl, Cadence PVS, floorplanning, LVS closure, Cadence ETS, Cadence Innovus, Signal Integrity, Physical Verification, VHDL, RTL-to-GDSII implementation, Synopsys ICC, Timing Closure, DRC, Placement
Skills:
routing, floor-planning, power distribution planning, LEC, LVS, MBR flows, VDSM process technology, Low Power physical design flows, Power-Gating, clock network planning, DRC, Timing Closure, Clock-Gating, placement and optimization
Skills:
EDA tools for physical design and verification, Floor Planning, digital design principles, CMOS processes, Timing Closure, multi-power domain analysis, low-power design techniques, clock design, RTL to GDS flows, Clock Tree Synthesis
Skills:
synopsys primetime , Asic Physical Design, Cadence innovus, Synopsys
Skills:
STA timing optimization, CTS and global clock distribution methods, power rollup methodology, Synthesis, Physical Verification, constraints generation, Place And Route, Timing Closure, Extraction, floorplanning
