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Principal Physical Design Engineer (6–10 Years)
Role Summary:
We are seeking a Principal Physical Design Engineer with 5 –10 years of ASIC physical design experience. The role involves driving the complete physical design flow from floorplanning to GDSII signoff, ensuring timing, power, area (PPA), and quality targets are achieved. You will also contribute to design methodology improvements and mentor junior engineers.
Key Responsibilities:
Required Skills & Qualifications:
To apply, send your resume at [Confidential Information]
Job ID: 151303833
Skills:
routing, power distribution planning, LEC, MBR flows, Floor Planning, design tools and flows, Low Power physical design flows, Power-Gating, clock network planning, Timing Closure, Clock-Gating, placement and optimization
Skills:
rc extraction , Timing ECO Implementation, Physical Design, Timing ECOs, Placement, floorplanning, Timing Closure, Routing and Optimization, Full-chip and Block-level Physical Implementation
Skills:
power integrity , UNIX, routing, Linux, Perl, Verilog, Shell scripting, Tcl, Cadence PVS, floorplanning, LVS closure, Cadence Innovus, Cadence ETS, Signal Integrity, Physical Verification, VHDL, Synopsys ICC, RTL-to-GDSII implementation, Timing Closure, DRC, Placement
Skills:
Shell, PYTHON, Static Timing Analysis, Tcl, Flex-H, power analysis, STA constraints, FinFET Dual Patterning nodes, Innovus, Physical Design, PD metrics dashboard scripts for QOR tracking, PNR flow from RTL to GDS flow, Multi-point CTS, Custom-CTS
Skills:
layout verification , static timing analysis, routing, Synthesis, coverage analysis, electrical rule checking, formal equivalence verification, Power Clock Distribution, physical design implementation, structural design checking, physical clock design, Place And Route, power and noise analysis, placing, static and dynamic power integrity, RTL to GDS, Floor Planning, Dft, EDA Tools, Timing Closure, multiple power domain analysis, Clock Tree Synthesis