Physical Design Engineer
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Job Title: Principal Engineer – Physical Design
Experience: 5–10 Years
Qualification: B.E./B.Tech/M.E./M.Tech in Electronics, Electrical Engineering, or equivalent
Job Description
We are looking for an experienced Principal Engineer – Physical Design to join our semiconductor engineering team. In this role, you will be responsible for the complete Physical Design flow, from floorplanning to GDSII convergence, while ensuring high-quality implementation and optimal Power, Performance, and Area (PPA).
Key Responsibilities
Drive end-to-end ASIC Physical Design from floorplanning to GDSII.
Perform floorplanning, placement, clock tree synthesis (CTS), routing, and timing closure.
Optimize designs for Power, Performance, and Area (PPA).
Implement Low Power methodologies such as Power Gating, Clock Gating, and Multi-Bit Register (MBR) flows.
Perform Logical Equivalence Check (LEC) and support DRC/LVS closure.
Debug and resolve physical design issues to achieve design convergence.
Enhance design methodologies, flows, and automation to improve productivity.
Collaborate with global engineering teams to ensure timely project delivery.
Mentor and guide junior engineers.
Required Skills
5–10 years of experience in ASIC Physical Design.
Strong expertise in RTL-to-GDSII implementation.
Experience with floorplanning, placement, routing, CTS, timing closure, and physical verification.
Hands-on experience with:
Synopsys ICC / PrimeTime
Cadence Innovus
Cadence ETS
Cadence PVS
Good understanding of Static Timing Analysis (STA), Signal Integrity, and Power Integrity.
Experience with DRC/LVS closure and advanced process technologies (VDSM).
Proficiency in TCL, Perl, and Shell scripting.
Working knowledge of Linux/UNIX and Verilog/VHDL.
Job ID: 151747947
Skills:
routing, Perl, Python, Tcl, Netlist to GDSII, power delivery IR-drop, Tempus, Cadence Innovus, LVS, Physical Verification, Floor Planning, Signal Integrity, primetime, Asic Physical Design, antenna checks, ERC, Timing Closure, DRC, Placement
Skills:
power integrity , Python, Routing, Perl, Tcl, IR drop, primetime, Design closure for setup hold timing, Cadence Innovus, LVS, SerDes PHY, DDR PHY, Timing Closure, StarRC, Placement, Timing signal integrity, Power Planning, floorplanning, DRC, Reliability requirements, Physical verification and signoff, Congestion analysis, PPA optimization, Synopsys ICC2
Skills:
EDA tools for physical design and verification, Floor Planning, digital design principles, CMOS processes, Timing Closure, multi-power domain analysis, low-power design techniques, clock design, Clock Tree Synthesis, RTL to GDS flows
Skills:
Tcl Scripting, Power-Aware PD implementation, Cadence Innovus, Synthesis and Constraints
Skills:
routing, power distribution planning, LEC, MBR flows, Floor Planning, design tools and flows, Low Power physical design flows, Power-Gating, clock network planning, Timing Closure, Clock-Gating, placement and optimization
