routing, Perl, Python, Tcl, Netlist to GDSII, power delivery IR-drop, Tempus, Cadence Innovus, LVS, Physical Verification, Floor Planning, Signal Integrity, primetime, Asic Physical Design, antenna checks, ERC, Timing Closure, DRC, Placement

power integrity , Python, Routing, Perl, Tcl, IR drop, primetime, Design closure for setup hold timing, Cadence Innovus, LVS, SerDes PHY, DDR PHY, Timing Closure, StarRC, Placement, Timing signal integrity, Power Planning, floorplanning, DRC, Reliability requirements, Physical verification and signoff, Congestion analysis, PPA optimization, Synopsys ICC2

EDA tools for physical design and verification, Floor Planning, digital design principles, CMOS processes, Timing Closure, multi-power domain analysis, low-power design techniques, clock design, Clock Tree Synthesis, RTL to GDS flows

Tcl Scripting, Power-Aware PD implementation, Cadence Innovus, Synthesis and Constraints

routing, power distribution planning, LEC, MBR flows, Floor Planning, design tools and flows, Low Power physical design flows, Power-Gating, clock network planning, Timing Closure, Clock-Gating, placement and optimization

rc extraction , Timing ECO Implementation, Physical Design, Timing ECOs, Placement, floorplanning, Timing Closure, Routing and Optimization, Full-chip and Block-level Physical Implementation

Shell, PYTHON, Static Timing Analysis, Tcl, Flex-H, power analysis, STA constraints, FinFET Dual Patterning nodes, Innovus, Physical Design, PD metrics dashboard scripts for QOR tracking, PNR flow from RTL to GDS flow, Multi-point CTS, Custom-CTS

layout verification , static timing analysis, routing, Synthesis, coverage analysis, electrical rule checking, formal equivalence verification, Power Clock Distribution, physical design implementation, structural design checking, physical clock design, Place And Route, power and noise analysis, placing, static and dynamic power integrity, RTL to GDS, Floor Planning, Dft, EDA Tools, Timing Closure, multiple power domain analysis, Clock Tree Synthesis

synopsys primetime , Asic Physical Design, Cadence innovus, Synopsys