Job Description:
Responsibilities include (but are not limited to):
- You will be participating in the leading-edge System-On-a-Chip (SoC) design projects using cutting-edge process technology nodes for various client applications.
- Execute complete physical design flow from RTL to GDS (synthesis, floorplan, power grid, place and route, clock tree synthesis), participating in design/architecture reviews to track design milestones.
- Evaluate and improve physical design methodologies to handle increasingly complex SoC/IP designs within aggressive, market-driven schedules.
- Actively work as part of a team both locally and with remote or multi-site teams.
- Actively assists full chip timing constraints development, full chip Static Timing Analysis, and timing signoff for a complex, multi-clock, multi-voltage SoC.
- Actively assists in full chip physical verification activities including DRC and LVS convergence & EM/IR convergence
Key Requirements:
- Minimum of Bachelor's Degree in Electrical engineering, Electronics Engineering, Computer Engineering, or a related discipline.
- Strong understanding of digital logic, VHDL/RTL representations, and Verilog.
- Proficiency in Perl, TCL, and Python for CAD flow automation and optimization.
- Experience with Synopsys EDA tools, including Fusion Compiler, PrimeTime, IC Validator, and VC LowPower.
- Successful completion and/or tapeouts on advanced FinFET technology nodes (16nm, 12nm, 7nm, 5nm, 3nm), including lowpower design methodologies
- Handson experience with placeandroute (PnR) including floorplanning & clock tree synthesis (CTS), physical verification, timing convergence and IR drop analysis.
- Experience in automated design flows and automated synthesis.
Additional Skills:
- Handson experience with fullchip or subchip Static Timing Analysis, timing constraint development, and timing closure.
- Experience with advanced signoff activities, including Lint, CDC, LEC, scan, and ECO flows.
- Experience in toplevel physical implementation.
- Experience with Cadence EDA tools, including Innovus, Tempus, Virtuoso, and Conformal LowPower.
- Experience with power analysis and power optimization techniques.
Equal Opportunity Statement
We are committed to creating a diverse and inclusive workplace. We encourage applications from all qualified individuals regardless of race, gender, age, sexual orientation, disability, or any other characteristic protected by law.
