Physical Design Engineer
Physical Design Engineer
Pride Global- Posted 16 hours ago
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Job Description
Physical Design Engineer
Employment type : Open to Perm & Contract
Working arrangement : Onsite
Location: Bayan Lepas, Penang
Salary Range : 4 – 6 Years (11-12k), 6 – 8 Years (13-15k), 8 – 10 Years (16-18k)
We are seeking a Physical Design Engineer with 4+ years of ASIC physical design experience to drive the complete Netlist-to-GDSII implementation flow for advanced technology nodes (7nm/5nm/3nm).
Key Responsibilities:
- Perform floorplanning, power planning, placement, CTS, routing, and timing closure.
- Analyze and fix setup/hold violations, signal integrity, IR-drop, and electromigration issues.
- Execute DRC, LVS, ERC, and antenna checks to achieve signoff-quality designs.
- Develop Tcl/Perl/Python scripts to automate physical design flows.
- Collaborate with cross-functional teams to deliver high-performance, low-power ASICs.
Requirements:
- Bachelor's or Master's degree in Electrical, Electronics, or Computer Engineering.
- 4+ years of ASIC Physical Design experience.
- Strong expertise in Netlist-to-GDSII flow, STA, CTS, and P&R.
- Hands-on experience with Synopsys (ICC2, PrimeTime) or Cadence (Innovus, Tempus).
- Proficiency in Tcl and/or Python scripting.
- Experience with advanced technology nodes (7nm/5nm/3nm) is preferred.
If you are interested, please send your updated resume to [Confidential Information] OR WA to +6011-45308817
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Key Skills
About Company
Skills:
Unix, Shell, Perl, Verilog, Automation Scripting, Python, Tcl, VHDL, Physical Design, EDA Tools, Low-Power Design Strategies
Skills:
Routing, Python Scripting, Calibre, Cadence Innovus, Fusion Compiler, floorplanning, ASIC SoC implementation, primetime, Physical Signoff, Synopsys ICC2, Block-level Physical Design, Signal Integrity analysis, Power Planning, Timing Closure, Placement Optimization
Skills:
Unix, python, perl, Linux, Tcl, Calibre, Back-End physical design EDA tools, large scale ASIC chip physical design, deep submicron ASIC design flow, Fusion Primetime
Skills:
Routing, Perl, Static Timing Analysis, Tcl, CTS, Cadence, LVS, Optimization, CAD Tools, Dfm, Parasitic Extraction, Physical Verification, Synthesis, PNR, Placement, DRC, Floor Planning, Mentor Graphics, Clock Tree Synthesis, IR drop analysis, Synopsys, GDSII
Skills:
Tcl, Python, EM, primetime, Si, SDC constraints, Ir, Innovus, Sta, ICC2