We are hiring an adaptive, self-motivated Physical Design Engineer to join our team. You'll help drive the capabilities in delivering high-performance, power-efficient silicon solutions. The Physical Design team values continuous technical innovation and supports professional growth through challenging projects and collaborative success. In this role, you will be responsible for full-chip floorplanning, physical implementation, timing closure, and power optimization across SoC designs.
Responsibilities:
Extensive hands-on experience in floorplanning, placement, clock tree synthesis (CTS), routing, timing closure, and physical verification.
Proficient in timing and SDC constraint generation and management; strong debugging skills are a plus.
Solid understanding of low-power design methodologies, including power-aware synthesis and place-and-route; familiarity with voltage domain checks is advantageous.
Proven experience in chip-level floorplanning, including feedthrough topology planning, repeater insertion, and top-level port/pin assignment.
Tapeout experience through multiple projects.
Qualifications:
Proficiency in EDA tools such as Design Compiler (DC) and Innovus/ICC2.
Skilled in Static Timing Analysis (STA) tools and techniques.
Strong grasp of floorplanning and layout techniques compliant with foundry design rules.
Experience with scripting languages including TCL, Perl, and Python.
Excellent communication skillswritten, verbal, and listening.
Strong interpersonal skills; adaptable, collaborative, and a dedicated team player.
