Principal Engineer - Design

PRINCIPAL ENGINEER - DESIGN

Location: Bayan Lepas, Pulau Pinang

Working Arrangement: Hybrid (3 days WFO + 2 days WFH)

We are seeking a highly experienced Principal Engineer – Design to lead ASIC design implementation activities from architectural understanding through timing signoff and tapeout. This role is responsible for driving RTL-to-GDS implementation, design optimization, DFT integration, low-power methodologies, and advanced process node development while providing technical leadership and mentoring to engineering teams. The ideal candidate will possess strong expertise in ASIC physical implementation, timing closure, design methodologies, and advanced semiconductor technologies.

Key Responsibilities:

• Lead ASIC design implementation activities from architectural understanding through timing signoff and tapeout.
• Develop, drive, and sign off RTL-to-GDS (RTL2GDS) implementation and flow improvement projects.
• Understand and interpret architectural and micro-architectural design intent.
• Optimize RTL design structures for effective and efficient synthesis implementation.
• Derive, review, validate, and sign off timing constraints with designers and architects.
• Implement Design-for-Test (DFT) solutions including scan insertion, compression, LOC/LOS, RAMBIST, and advanced DFT techniques.
• Support low-power design implementation through architectural feedback, vector-driven optimization, and leakage/dynamic power reduction techniques.
• Provide technical leadership, guidance, and reviews for team members in solving complex design challenges.
• Contribute technical innovations through patents, trade secrets, and design methodologies.
• Drive Best-in-Class design implementation processes, benchmarking, and new methodology development.
• Document design implementation approaches, considerations, challenges, and solutions using corporate templates.
• Complete audit documentation, checklists, reviews, and closures in compliance with Design Control Procedures (DCP).
• Record issues, solutions, and review outcomes in project ticketing systems (PEPS) and CAD ticketing systems (JIRA).
• Collaborate with project managers, product development teams, ATPG teams, and CAD/TA teams on project and methodology-related matters.

Requirements:

·      Bachelor's or Master's Degree in Electrical Engineering, Electronics Engineering, or related disciplines.

·      Have 12–16 years of ASIC IC Design experience.

·      Strong expertise in Cadence Genus or Synopsys Design Compiler.

·      Strong expertise in Cadence Tempus or Synopsys PrimeTime.

·      Strong problem-solving, analytical, and critical-thinking skills.

·      Ability to provide technical leadership and mentorship to engineering teams.

·      Good communication and stakeholder management skills.

Added Advantages:

·      Exposure to advanced process nodes of 7nm and below.

·      Familiarity with SystemVerilog fundamentals and coding.

·      Strong scripting skills in Perl, TCL, Shell, or Python.