Senior Design Verification Engineer

Experience: 5+ years

Job Summary

We are looking for a Senior Verification Engineer experienced in ASIC-SoC functional verification to develop UVM-based environments, execute verification plans, debug issues, and drive verification closure.

Key Responsibilities

Develop verification plans, testbenches, test cases, sequences, scoreboards, and coverage models.

Build and maintain SystemVerilog/UVM verification environments.

Perform constrained-random, functional, and regression testing.

Develop SystemVerilog assertions (SVA) and track functional/code coverage.

Debug simulation failures and work closely with RTL/design teams.

Drive verification closure and mentor junior engineers.

Required Skills

5+ years of ASIC/SoC/IP verification experience.

Strong SystemVerilog and UVM skills.

Experience with constrained-random and coverage-driven verification.

Good knowledge of SVA, functional/code coverage, and regression.

Strong digital design/RTL understanding and debugging skills.

Scripting experience in Python, Perl, or Tcl.

Experience with protocols such as AMBA, PCIe, DDR, Ethernet, USB, or MIPI.

Good to Have

SoC-level verification, formal/emulation, or C/C++ experience.

Exposure to CI/CD-based verification.

Education

Bachelor's/Master's degree in EE, Electronics, Computer Engineering, or related field.