perform signal integrity and power delivery of high-speed interfaces.
Support electrical engineers by performance signal and power simulations throughout the package design cycle
Analyze electrical results such as S-Parameters, IR drop, Loop inductance etc.
Summarize results and recommendations in proper reports.
Specific simulation tools that are used as part of the signal integrity analysis process include ANSYS Layout, ANSYS Q3D, Cadence PowerDC, and Power-SI.
Requirement:
Should possess a Bachelor, master's in electrical/ Electronics Engineering or relevant disciplines with 3-5 years in the related fields
Proven knowledge in the use of simulation and modeling tools such as, ANSYS 3D Layout, Q3D, PowerDC & Power SI to develop signal and power integrity design recommendations.
Experience in the electrical analysis and design of high-speed interconnects for Technology interfaces such as DDR, SerDEs, PCIe and USB - Added advantage.
Understanding of the package design processes - Added advantage.
