Fpga, Perl, Python, Emulation, RTL, Uvm, systemverilog

Verilog, Ethernet, Python, Pcie, DDR, Modelsim, Synopsys VCS, VHDL, UCIe, Uvm, formal verification, Cadence Incisive

Computer Architecture, Vcs, DDR, Pcie, Perl, Ethernet, Python, Verdi, ARM-based SoC architecture, CHI, Xcelium, SystemVerilog UVM, Axi, APB, HBM, Questa, AHB, SVA

testability , systemverilog, SoC IP verification methodologies, Uvm, DFX DFT concepts, ATPG, multi-level verification

bandwidth management , Machine Learning, Artificial Intelligence, Microprocessor Cores, full verification life cycle, vector processing units, industry-standard simulators, AI ML Accelerators, systemverilog, hierarchical memory subsystems, revision control systems, Specman E, constrained-random verification environments, Verification, IP subsystem SoCs, packet processing, congestion control, regression systems, Debug

Test Plan Creation, Debugging, Python, Perl, VIP integration, testbench architecture, Uvm, verification methodologies, scoreboarding, systemverilog, coverage-driven verification, execution and review, assertions, regression management, debug flows, functional coverage

Tcl, Python, Perl, systemverilog, Functional Verification, UVM methodology, High-speed networking interfaces, Coverage-driven verification, Ethernet IPs, Emulation platforms or FPGA prototyping

Spi, I2c, Uart, Pcie, Usb, Noc, cdc, SoC IP Design, AMBA protocols, Network on Chip

Tcl, Python, Perl, Shell, Debugging RTL verification issues, Assertions SVA, Functional Verification, UVM methodology, systemverilog, Coverage-driven verification

Verilog, Tcl, Python, Perl, Uvm, VHDL, systemverilog