Pcie, System Verilog, Python, Systemc, Hybrid test benches, MDV, DV signoffs, SV, Uvm, UCIe, Axi, CDV

Usb, DDR, Perl, Pcie, Ethernet, Python, Tcl, Uvm, coverage-driven verification, systemverilog, digital design RTL understanding, AMBA, MIPI, SVA

C, Perl, Python, Low power verification methods, FPGA emulator software environments, Emulation platforms, Uvm, systemverilog, Industry standard I/O interfaces, AMBA bus protocols, RTL development environments, Baremetal processor environments, Formal verification methods, UPF based low power verification, Transaction level modeling

Vcs, Pcie, Python, Tcl, Xcelium, Uvm, systemverilog, APB, Questa, AXI4, AHB, SVA

Gpio, DDR, Pcie, Uart, I2c, Spi, UVM methodology, HBM, CXL, QSPI, I3C, systemverilog

Nvme, Pcie, Ethernet, System Verilog, Uvm, Axi, APB, CXL, Industry-standard simulation and debug tools, UCIe, AHB

Usb, Ovm, Pcie, Ethernet, Test and coverage plan, Verification environment, Assertion checkers, Uvm, MIPI, Validation plan, System Verilog HVL, Coverage and scenario creation, VMM Test Harness

code coverage , Oops, Usb, Networking, Cpu, DDR, Pcie, Verilog, Ethernet, Arm, LINT, cdc, SV, SV METH, C tests, Axi, AMBA, spyglass, VHDL, SoC Verification, Graphics, RTL Coding, AHB