Senior Design Verification Engineer
Senior Design Verification Engineer
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Job Description
Position: Senior Design Verification Engineer (SoC / PCIe / CXL)
Location: Pune / Bangalore / Hyderabad / Ahmedabad
Experience: 7+ Years
Employment Type: Full-time
About The Opportunity
Best NanoTech is looking for a seasoned Senior Design Verification Engineer.
We are looking for a hands-on technical leader to manage SoC verification efforts for next-generation chips involving high-speed protocols like CXL, HBM, and PCIe.
Key Responsibilities
If you are ready to take ownership of complex SoC projects, apply via LinkedIn or send your resume directly to [Confidential Information].
#DesignVerification #SoC #PCIe #CXL #HBM #VLSIJobs #Semiconductor #BestNanoTech #Hiring
Location: Pune / Bangalore / Hyderabad / Ahmedabad
Experience: 7+ Years
Employment Type: Full-time
About The Opportunity
Best NanoTech is looking for a seasoned Senior Design Verification Engineer.
We are looking for a hands-on technical leader to manage SoC verification efforts for next-generation chips involving high-speed protocols like CXL, HBM, and PCIe.
Key Responsibilities
- Lead Verification Efforts: Manage and execute end-to-end SoC Design Verification plans for complex projects, ensuring zero-bug silicon.
- Strategy & Architecture: Develop comprehensive verification strategies, test plans, and robust test benches.
- Protocol Verification: Verify high-speed interfaces (PCIe, Ethernet, CXL, MIPI, DDR, HBM) and standard peripherals (I2C/I3C, SPI, UART, GPIO, QSPI).
- Coverage Closure: Analyze and implement SystemVerilog Assertions (SVA) and drive coverage closure (Code, Toggle, Functional).
- Timeline Management: Demonstrate strong ownership of project goals, ensuring critical deadlines are met with high quality.
- Experience: 7+ years of relevant industry experience in VLSI/ASIC Verification.
- Core Skills: Strong command over SystemVerilog and UVM methodology.
- Protocol Knowledge: Deep understanding of high-speed protocols (PCIe, CXL, DDR/HBM) is mandatory.
- Debugging: Proficiency in debugging complex SoC scenarios.
- Experience with Gate-Level Simulations (GLS).
- Power-Aware Verification expertise using UPF and Xprop.
- Work on the bleeding edge of technology (CXL, HBM, 3nm nodes).
- Flexible location options across major tech hubs (Pune, BLR, Hyd, Ahd).
- Collaborative culture with direct mentorship from industry veterans.
If you are ready to take ownership of complex SoC projects, apply via LinkedIn or send your resume directly to [Confidential Information].
#DesignVerification #SoC #PCIe #CXL #HBM #VLSIJobs #Semiconductor #BestNanoTech #Hiring
More Info
About Company
Skills:
Pcie, System Verilog, Python, Systemc, Hybrid test benches, MDV, DV signoffs, SV, Uvm, UCIe, Axi, CDV
Skills:
Fpga, Perl, Python, Emulation, RTL, Uvm, systemverilog
Skills:
Usb, DDR, Perl, Pcie, Ethernet, Python, Tcl, Uvm, coverage-driven verification, systemverilog, digital design RTL understanding, AMBA, MIPI, SVA
Skills:
SystemVerilog Assertions (SVA), test environments , Gate-Level Simulation (GLS), Test Cases, Low power debug, Constrained-random verification environments, Uvm, systemverilog, Verification test benches, Formal tools, Verification methodologies, Coverage measures, formal verification
Skills:
Vcs, functional coverage assertions, Questa, Uvm, SVA, systemverilog