power integrity , UNIX, routing, Linux, Perl, Verilog, Shell scripting, Tcl, Cadence PVS, floorplanning, LVS closure, Cadence Innovus, Cadence ETS, Signal Integrity, Physical Verification, VHDL, Synopsys ICC, RTL-to-GDSII implementation, Timing Closure, DRC, Placement

cadence spectre , Perl, Python, AMS verification, JEDEC LPDDR DDR specifications, StarRC, Circuit simulation tools, Mixed-signal circuit design, Cadence ADE, DDR protocols, Analog Circuit Design

bandgap references , Dll, DDR, ADE, analog timing analysis, Design Verification, transistor-level simulation, analog RTL modeling, power delivery solutions, Spectre, Pll, high-speed clock distribution circuits, clock generation, SERDES, analog mixed-signal circuit design, Cadence Virtuoso, LDOs

Dll, analog design timing analysis, DDR IO, Serder IO, LDO, ADE Cadence tools, Analog RTL modeling, Bandgap power-delivery simulation, Pure complex analog circuit, high-speed clk distribution, Pll, high speed IO

C, Verilog, Matlab, Ise, Verdi, Mentor ModelSim, Synopsys VCS, quartus, Dft, VHDL, Vivado, Cadence NC-Verilog, Timing Closure

synopsys primetime , Asic Physical Design, Cadence innovus, Synopsys