System Verilog, Assertions SVA, AMBA protocols AXI AHB APB, ARM Cortex-M33, Peripheral interfaces SPI UART I2C I2S TDM, AMS co-sim, RISC-V SoCs, Uvm, Functional coverage, Mixed-signal verification environments, Low-power verification UPF CPF

System Verilog, Cadence Xcelium, HBM4, DRAM Memory Controller IPs, Cadence, verification management tools, Questa Formal Mentor, assertion-based verification, Uvm, Synopsys VCS, Crypto, Synopsys JasperGold, DDR5, VC Formal, LPDDR6, Network-on-Chip NoC

Verification methodologies such as UVM, Understanding of StarRC Calibre parasitic extraction flow, NAND Flash memory design, Test Bench development in System Verilog

code coverage , SoC Verification, MCU Verification, Uvm, Functional Coverage, Assertion Coverage

System Verilog, CPU Core Verification, Uvm, Coverage models, Constrained-random tests, Scoreboards, Checkers, Testbenches

Tcl, System Verilog, Python, Perl, Vcs, Questa, Uvm, Modelsim

Usb, C, C++, Debugging, Test Plan, Object Oriented Programming, Writing Test Cases, Oop, DDR, Ethernet, Pcie, Perl, Tcl, Function coverage, Coverage driven verification, Uvm, IP Subsystem SOC ASIC Verification, Axi, Code coverage analysis, CXL, Test bench development, Simulation, System-Verilog

Cadence - Virtuoso, Perl, Python, Tcl, Spice Simulator, Unix environment and shell scripting, SV and UVM testbench development, Verilog-AMS, Verilog Hdl, Verilog-D, Verilog-A