Unix, Shell, Perl, Verilog, Automation Scripting, Python, Tcl, VHDL, Physical Design, EDA Tools, Low-Power Design Strategies

Python, Tcl, Sta, Asic Physical Design, CTS, primetime, Netlist-to-GDSII flow, Cadence Innovus, Tempus, Synopsys ICC2

rc extraction , Timing ECO Implementation, Timing ECOs, Physical Design, floorplanning, Timing Closure, Placement, Routing and Optimization, Full-chip and Block-level Physical Implementation

layout verification , static timing analysis, routing, Synthesis, coverage analysis, electrical rule checking, formal equivalence verification, physical design implementation, Power Clock Distribution, structural design checking, physical clock design, Place And Route, custom IP and SoC designs, power and noise analysis, placing, Floor Planning, static and dynamic power integrity, Dft, EDA Tools, Timing Closure, multiple power domain analysis, Clock Tree Synthesis

Unix, python, perl, Linux, Tcl, Calibre, Back-End physical design EDA tools, large scale ASIC chip physical design, deep submicron ASIC design flow, Fusion Primetime

Tcl, Python, EM, primetime, Si, SDC constraints, Ir, Innovus, Sta, ICC2