Python, Ovm, Perl, Uvm, Gate-level verification

System Verilog, C, Python, Debugging, C++, System simulation models, Uvm, Test benches, FPGA design verification, Verification tools and methodologies, IP verification plans

C Programming, Debugging, Problem-solving, SoC-level verification, UVM-based verification environments

Tcl, Python, Perl, formal coverage, Uvm, Cadence JasperGold, Synopsys VC Formal, systemverilog, FPV connectivity checking, register verification, equivalence checking

Tcl, Jtag, Python, Perl, Git, SVA, MBIST, Uvm, DFT Architectures, Functional Coverage, systemverilog, Regression Automation, Scan, LBIST

assertion based verification , Debugging Tools, Scripting Languages, systemverilog, Uvm, Testbench Development, FPGA Prototyping, coverage analysis, Design Simulation, Design Verification, Asic verification, SoC Verification