Clock Tree Synthesis (CTS), Routing, Python Scripting, Perl, Tcl, floorplanning, Physical Signoff, Power Planning, Physical Design, Placement, Timing Closure, ASIC SoC implementation

redhawk , Tcl Scripting, primetime, Logic Synthesis, Fusion Compiler, ICC2, Conformal, LVS, Physical Design, electro-migration checks, Calibre, custom polygon editing, Formal equivalence, CPU physical design, floorplanning, Dce, StarRCXT, Cadence Tools, Timing Verification, Timing Closure, DRC, DCT, ICV, Noise cross-talk OCV analysis

EDA Tools, Calibre, primetime, Fusion Compiler, ASIC SoC Physical Design, ICC2, Unix Linux environments

layout verification , static timing analysis, routing, Synthesis, coverage analysis, electrical rule checking, formal equivalence verification, physical design implementation, Power Clock Distribution, structural design checking, physical clock design, Place And Route, custom IP and SoC designs, power and noise analysis, placing, Floor Planning, static and dynamic power integrity, Dft, EDA Tools, Timing Closure, multiple power domain analysis, Clock Tree Synthesis

ASIC Design, IC design, ASIC Tape out, VDSM