Design Verification Engineer

We are looking for talents with a passion for modern, complex processor architecture, digital design, and verification in general for our client's company. You will be a team player who has excellent communication skills and collaborating with other engineers located in different sites/time zones. You will also obtain strong analytical and problem-solving skills and are willing to learn and ready to take on problems.

Key Responsibilities:

• Design verification of Analog/HSIO features
• Build testbench components to support the next generation of NBIO IPs
• Estimate the time required to write the new feature tests and any required changes to the test environment
• Develop, maintain, and improve test libraries to support IP level testing
• Test coverage and test cost reduction analysis
• Provide technical support to SoC and Post-Si teams to ensure successful bring up and enhance yield learning

Requirements:

• Bachelor's or master's degree in related engineering discipline
• Must have experience in PCIE/DDR/USB/UCIE/CXL protocols for HSIO testing
• Understanding of Test methodologies and design verification experience on IO Loopback, HSIO testing, PRBS, etc
• Experienced with Verilog, System Verilog, C, and C++
• Developing UVM based verification frameworks and testbenches, processes and flows
• Experience with VCS simulation tool, Perl/Shell scripting, and Verilog RTL design
• Experience in debug test failures to determine the root cause and work with design engineers to resolve design defects and correct any test issues will be a plus point
• Experience with ATE (Automatic Test Equipment) - ATE test pattern & test flow development, debug, test, and characterization is preferred
• Good communication skill in English, and fluency in Mandarin will be a plus point, due to business need of handling China or Taiwan stakeholders