Physical Design Engineer
Physical Design Engineer
Russell Tobin- Posted 2 hours ago
- Be among the first 10 applicants
Job Description
Key Responsibilities:
- Working on 10nm/7nm/5nm or lower nodes designs with various customers.
- Responsible to understand and develop flow/methodology using Perl/TCL programming for PnR activities (Floor planning, Placement, CTS, and Routing).
- Expertise in solving lower node technology related problems for critical designs to achieve desired performance, area, and power targets.
- Provide training and technical assistance to peers/customers.
Preferred Experience:
- Experience in Top/Block level ASIC PnR implementation (RTL to GDSII).
- Tape-out experience in lower nodes like 3nm, 5nm, 7nm, 10nm and above.
- Hands-on experience in Synthesis, Floor planning, Placement, Clock tree synthesis, Optimization, Routing, Parasitic Extraction, Static Timing Analysis, IR drop analysis, Physical Verification (DRC/LVS/DFM, chip finishing) and Sign Off.
- Excellent communication and presentation skills, experience in collaborating with global teams.
- Experience in hierarchical designs and/or Low Power implementation is an advantage.
- Working experience on CAD tools from Synopsys, Cadence and Mentor Graphics tool set.
- Must be an initiative-taker and be able to drive tasks independently and efficiently to completion.
- Ability to provide mentorship and guidance to junior engineers and be an effective team player.
- Min 3 years of experience as PDE.
- Preferred Tool for PD:
Cadence Innovus, Tempus, Calibre
Innovus tool is the primary requirement
More Info
Job Type:
Industry:
Function:
Employment Type:
Key Skills
Cadence Innovus
Tempus
Calibre
IR drop analysis
Sign Off
Chip finishing
RTL to GDSII
Tape-out
DRC
Hierarchical designs
Low Power implementation
CAD tools from Synopsys
About Company
Skills:
Unix, Shell, Perl, Verilog, Automation Scripting, Python, Tcl, VHDL, Physical Design, EDA Tools, Low-Power Design Strategies
Skills:
Python, Tcl, Sta, Asic Physical Design, CTS, primetime, Netlist-to-GDSII flow, Cadence Innovus, Tempus, Synopsys ICC2
Skills:
rc extraction , Timing ECO Implementation, Timing ECOs, Physical Design, floorplanning, Timing Closure, Placement, Routing and Optimization, Full-chip and Block-level Physical Implementation
Skills:
layout verification , static timing analysis, routing, Synthesis, coverage analysis, electrical rule checking, formal equivalence verification, physical design implementation, Power Clock Distribution, structural design checking, physical clock design, Place And Route, custom IP and SoC designs, power and noise analysis, placing, Floor Planning, static and dynamic power integrity, Dft, EDA Tools, Timing Closure, multiple power domain analysis, Clock Tree Synthesis
Skills:
Unix, python, perl, Linux, Tcl, Calibre, Back-End physical design EDA tools, large scale ASIC chip physical design, deep submicron ASIC design flow, Fusion Primetime