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Physical Design Engineer
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Physical Design Engineer
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Job Description
Physical Design Engineer
Location: Penang, Malaysia
Employment type: Permanent
We are seeking a Physical Design Engineer with at least two years of relevant SoC/ASIC experience to support advanced chip design projects, from synthesis through to GDS delivery.
Key responsibilities
- Execute block- and subsystem-level physical implementation for advanced SoC/ASIC designs.
- Perform synthesis, floorplanning, clock tree synthesis, static timing analysis (STA), signal integrity analysis, EM/IR analysis, ECO implementation and formal equivalence verification.
- Conduct physical verification, including DRC, density, antenna and LVS checks.
- Carry out pathfinding, debugging and regression runs to deliver high-quality designs.
- Collaborate with product/IP architects, logic design engineers, DFX owners and design automation engineers to meet project milestones.
The role may offer opportunities for short- to medium-term overseas travel or relocation, depending on project requirements.
Requirements
- Bachelor's or Master's degree with a minimum of two years of relevant industry experience in SoC/ASIC physical design.
- Familiarity with block- or subsystem-level implementation flows, from synthesis to GDS.
- Hands-on experience with industry-standard EDA tools from Cadence and/or Synopsys.
- Experience across the physical design and verification activities listed above.
- Practical knowledge of clock-gating and power-gating methodologies.
- Proficiency in scripting or programming using languages such as Shell, Tcl, Perl, Python or C++, and familiarity with Linux.
- Ability to work independently and collaborate effectively within a multidisciplinary team.
Added advantages
- Advanced proficiency with Cadence or Synopsys tools.
- Specialisation in STA or experience with high-speed PHY design.
- Ability to communicate professionally in Mandarin or Japanese.
More Info
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Key Skills
About Company
Skills:
Clock Tree Synthesis (CTS), Routing, Python Scripting, Perl, Tcl, floorplanning, Physical Signoff, Power Planning, Physical Design, Placement, Timing Closure, ASIC SoC implementation
Skills:
redhawk , Tcl Scripting, primetime, Logic Synthesis, Fusion Compiler, ICC2, Conformal, LVS, Physical Design, electro-migration checks, Calibre, custom polygon editing, Formal equivalence, CPU physical design, floorplanning, Dce, StarRCXT, Cadence Tools, Timing Verification, Timing Closure, DRC, DCT, ICV, Noise cross-talk OCV analysis
Skills:
EDA Tools, Calibre, primetime, Fusion Compiler, ASIC SoC Physical Design, ICC2, Unix Linux environments
Skills:
layout verification , static timing analysis, routing, Synthesis, coverage analysis, electrical rule checking, formal equivalence verification, physical design implementation, Power Clock Distribution, structural design checking, physical clock design, Place And Route, custom IP and SoC designs, power and noise analysis, placing, Floor Planning, static and dynamic power integrity, Dft, EDA Tools, Timing Closure, multiple power domain analysis, Clock Tree Synthesis
Skills:
ASIC Design, IC design, ASIC Tape out, VDSM