Unix, Automation Scripting, Shell, Perl, Verilog, Python, Tcl, power analysis, Low-Power Design Strategies, VHDL, Physical Design, EDA Tools

Python, Tcl, Sta, Asic Physical Design, CTS, primetime, Netlist-to-GDSII flow, Tempus, Cadence Innovus, Synopsys ICC2

power integrity , UNIX, routing, Perl, Linux, Verilog, Shell scripting, Tcl, Cadence PVS, DRC LVS closure, floorplanning, Cadence Innovus, Cadence ETS, Signal Integrity, Physical Verification, VHDL, RTL-to-GDSII implementation, Synopsys ICC, Timing Closure, Placement

power integrity , Python, Routing, Perl, Tcl, IR drop, primetime, Design closure for setup hold timing, Cadence Innovus, LVS, SerDes PHY, DDR PHY, Timing Closure, StarRC, Placement, Timing signal integrity, Power Planning, floorplanning, DRC, Reliability requirements, Physical verification and signoff, Congestion analysis, PPA optimization, Synopsys ICC2

Shell, PYTHON, Static Timing Analysis, Tcl, Flex-H, power analysis, STA constraints, FinFET Dual Patterning nodes, Innovus, Physical Design, PD metrics dashboard scripts for QOR tracking, PNR flow from RTL to GDS flow, Multi-point CTS, Custom-CTS

rc extraction , Timing ECO Implementation, Physical Design, Timing ECOs, Placement, floorplanning, Timing Closure, Routing and Optimization, Full-chip and Block-level Physical Implementation

layout verification , static timing analysis, routing, Synthesis, coverage analysis, electrical rule checking, formal equivalence verification, Power Clock Distribution, physical design implementation, structural design checking, physical clock design, Place And Route, power and noise analysis, placing, static and dynamic power integrity, RTL to GDS, Floor Planning, Dft, EDA Tools, Timing Closure, multiple power domain analysis, Clock Tree Synthesis